The present embodiments relate to electronic processors such as microprocessors or digital signal processors (“DSPs”), and are more particularly directed to providing such a processor operable in response to an instruction to efficiently shift a data argument in response to respective left and right shift count indicators.
Electronic processors including microprocessors and DSPs have become prevalent in numerous applications, including uses for devices in personal, business, and other environments. Demands of the marketplace affect many aspects of processor design, including factors such as device power consumption and speed. As a result, constant evaluation is performed by processor designers in an effort to provide improvements in these and other factors. The present embodiments also endeavor toward this end.
The present embodiments are directed to providing an improved processor functional unit for purposes of rotating a data argument. Rotation of a data argument is intended to cover the instance where data is to be shifted twice, once in a first direction and then thereafter in an opposite direction. Thus, two possibilities exist, namely, a right shift followed by a left shift or a left shift followed by a right shift. Two such successive shifts may be required in various instances, where by way of example the present commercially available DSPs sold by Texas Instruments Incorporated under the TMS320C6xxx family include an EXTRACT instruction in the DSP instruction set, and that instruction calls for two successive and opposite-direction shifts. The use of such operations is typically beneficial to manipulate or isolate a portion of data within a data word, where the word in contemporary processors is often a 32-bit data argument. Further, these two shifts can be used with additional operations, such as arithmetic or logical operations with another data argument, in order to achieve an intended result. In any event, in previous processors, such operations required either the use of two successive shift instructions, or the use of the EXTRACT instruction, with either approach being executed in the processor by performing a complete shift in one direction followed by another complete shift in the opposite direction. In this regard, either two independent operations are expended, one for each shift, or the two shifts might be executed simultaneously, thereby requiring however the complexity of two different 32-bit shifters (i.e., one for each of the two shifts). Additional delay and/or additional complexity, such as that required by these prior art approaches, are considered drawbacks in contemporary processor design.
In view of the above, there arises a need to address the drawbacks of the prior art, as is achieved by the preferred embodiments described below.